************************************************************************************************* ************************************************************************************************* ** ** ** File.................: a2d.asm ** ** ** ** Copyright 2002 by Kerwin Lumpkins ** ** ** ** This program sets up port b, pin 7 to be an a2d channel, takes a sample about every second * ** and displays the digital representation on port A. If you have led's on port a you will ** a visual representation of the 8 bit digital rep of the analog voltage on port B7 ************************************************************************************************* ************************************************************************************************* * Equates * * * * These are the locations of various MCU registers for the 68HC908GPXX MCU. * ************************************************************************************************* pta equ $00 ;port a data register ptb equ $01 ;port b data register ptc equ $02 ;port c data register ptd equ $03 ;port d data register pte equ $08 ;port e data register ddra equ $04 ;port a data direction register ddrb equ $05 ;port b data direction register ddrc equ $06 ;port c data direction register ddrd equ $07 ;port d data direction register ddre equ $0C ;port e data direction register scc1 equ $13 ;sci control register 1 scc2 equ $14 ;sci control register 2 scc3 equ $15 ;sci control reg 3 scs1 equ $16 ;sci status reg 1 scs2 equ $17 ;sci status reg 2 scdr equ $18 ;sci data reg scbr equ $19 ;sci baud rate reg config2 equ $1E ;sci config reg 2 config1 equ $1f ;config register 1 t1sc equ $20 ;timer 1 status and control reg t1cnth equ $21 ;timer 1 counter reg high t1cntl equ $22 ;timer 1 counter reg low t1modh equ $23 ;timer 1 modulo reg high t1modl equ $24 ;timer 1 modulo reg low t1sc0 equ $25 ;timer 1 channel 0 status and control reg t1ch0h equ $26 ;timer 1 channel 0 reg high t1ch0l equ $27 ;timer 1 channel 0 reg low adscr equ $3C ;a2d status and control reg adr equ $3D ;a2d data register adclk equ $3E ;a2d clock register ram equ $40 ;start of ram flash equ $8000 ;start of flash ($b000 for GP20, $8000 for GP32) *******************Specific to this application equates************************ org ram a2dvalue rmb 1 ;variable to hold the converted value secs rmb 1 ;variable used in wait routine ************************************************************************************************* * Interrupt Vectors * * * * Go to interrupt vector area and fill with init to prevent any interrupts from affecting the * * code. * ************************************************************************************************* org $ffdc ;fill interrupt vectors fdb init ;timebase vector address fdb init ;conversion complete vector address fdb init ;keyboard pin vector address fdb init ;sci transmit complete, empty vector address fdb init ;sci idle or receiver full vector address fdb init ;sci parity, framing, noise, overrun error address fdb init ;spi transmitter empty vector address fdb init ;spi full,over,fault vector address fdb init ;tim2 overflow vector address fdb init ;tim2 channel 1 vector address fdb init ;tim2 channel 0 vector address fdb init ;tim1 overflow vector address fdb init ;tim1 channel 1 vector address fdb init ;tim1 channel 0 vector address fdb init ;cgm (pll) vector address fdb init ;IRQ pin vector address fdb init ;swi instruction vector address fdb init ;reset vector address ************************************************************************************************* * Initialization * * * * This section clears variables, and sets up internal registers for the microcontroller * ************************************************************************************************* org flash ;start main code at the beginning of flash init mov #$01,config2 ;Osc disable on stop, SCI clock source internal mov #$01,config1 ;COP disabled, all other default (see p142) ldhx #$0240 ;load HX with the end of memory location txs ;put the stack pointer at the end of memory clra ;clears A, X, and H regs clrx clrh mov #$1F,ADSCR ;inits the A2D port ints disabled,one conversion, adc pwr off mov #$30,ADCLK ;sets a 1 MHz ADC clock assuming a 9.8304 MHz ext oscillator **************** memory definitions ***************************** clr pta ;clears out port a mov #$FF,ddra ;sets port a for all output loop: mov #$07,ADSCR ;get voltage on port B, pin 7 (of GP32) loop_convert: brset 7,ADSCR,got_value ;loop until the conversion complete bit is set bra loop_convert got_value: lda adr ;load A with the converted value from data reg sta a2dvalue ;move it to ram variable sta pta ;and load it to port A lda #!20 ;2 second jsr waits clr pta ;after delay, clear out port a and get another reading bra loop waits: ***** delay for number of .1 seconds passed in A reg sta secs ;save teh .1 sec counter wsloop: lda #!100 ; .1 sec = 100 ms bsr waitms ; wait that long dec secs ; dec .1 sec counter bne wsloop ; loop until 0 rts waitms: ****** delay for number of miliseconds passed in A reg wmsolp: ldx #!250 ;number of loops for 1 ms delay wmsilp: decx ;decrement nop ; no op for a bit bne wmsilp ; dec deca bne wmsolp ; loop for spec'd number of ms rts